1. Field of the Invention
This invention relates to a technology of an electric circuit. Also, this invention relates to a technology of a semiconductor apparatus. Further, this invention belongs to a technical field of a semiconductor apparatus having an electric circuit as represented by a source follower circuit, a differential amplifier, a sense amplifier, an operational amplifier etc., a signal line drive circuit and a photoelectric transducer device.
2. Description of the Related Art
An integrated circuit (IC) which has been widely used in portable telephones and portable terminals etc. in these years is of a structure that several hundreds of thousands to several million transistors and resistors were formed on a silicon substrate of approximately 5 mm square, and plays an important role in miniaturizing an apparatus and increasing reliability of an apparatus and in mass production of apparatuses.
Then, when an electric circuit to be used in the integrated circuit (IC) etc. is designed, in many cases, an amplifier circuit having a function for amplifying a voltage and an electric current of a signal with small amplitude is designed. The amplifier circuit has been widely used, since it is an indispensable circuit for preventing the generation of distortion, thereby operating the electric circuit stably.
Here, as one example of the amplifier circuit, a structure of a source follower circuit and its operation will be described. Firstly, a structural example of the source follower circuit is shown in FIG. 5A, and an operation in a steady state will be described. Then, by use of FIGS. 5B and 5C, an operating point of the source follower circuit will be described. Finally, an example of the source follower circuit of a structure different from FIG. 5A is shown in FIG. 6, and an operation in a transient state will be described.
Firstly, by use of the source follower circuit of FIG. 5A, the operation in the steady state will be described.
In FIG. 5A, reference numeral 11 designates a n-channel type amplifying transistor and reference numeral 12 designates a n-channel type biasing transistor. In addition, the amplifying transistor 11 and the biasing transistor 12 shown in FIG. 5A are of n-channel type but, they may be configured by use of p-channel type transistors. Also, here, for the purpose of simplicity, it is assumed that the amplifying transistor 11 and the biasing transistor 12 are the same in its characteristic and size and further, an electric current characteristic is also ideal. In sum, it is assumed that, even if a voltage between a source and a drain of the amplifying transistor and the biasing transistor 12 varies, an electric current value in a saturation region does not vary.
Also, a drain region of the amplifying transistor 11 is connected to a power supply line 13, and a source region is connected to a drain region of the biasing transistor 12. A source region of the biasing transistor 12 is connected to a power supply line 14.
A bias electric potential Vb is applied to a gate electrode of the biasing transistor 12. Then, a power supply electric potential Vdd is applied to the power supply line 13, and a ground electric potential Vss is applied to the power supply line 14.
In the source follower circuit shown in FIG. 5A, a gate electrode of the amplifying transistor 11 becomes an input terminal, and an input electric potential Vin is applied to the gate electrode of the amplifying transistor 11. Also, a source region of the amplifying transistor 11 becomes an output terminal, and an electric potential of a source region of the amplifying transistor 11 becomes an output electric potential Vout. The bias electric potential Vb is applied to the gate electrode of the biasing transistor 12, and it is assumed that, when the biasing transistor 12 operates in a saturation region, an electric current shown by Ib flows. At this time, since the amplifying transistor 11 and the biasing transistor 12 are connected serially, electric currents of the same amount flow through the both transistors. That is, when the electric current Ib flows through the biasing transistor 12, the electric current Ib also flows through the amplifying transistor 11.
Here, the output electric potential Vout in the source follower circuit will be calculated. The output electric potential Vout becomes a value which is smaller than the input electric potential Vin by just the voltage Vgs1 between the gate and the source of the amplifying transistor 11. At this time, a relation of the input electric potential Vin, the output electric potential Vout and the voltage Vgs1 between the gate and the source satisfies the following equation (1).Vout=Vin−Vgs1  (1)
Then, since, in case that the amplifying transistor 11 operates in the saturation region, the electric current Ib flows through the amplifying transistor 11, it is necessary that the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is equal to the bias electric potential Vb. Then, the following equation (2) is achieved. However, the equation (2) is achieved only when the amplifying transistor 11 and the biasing transistor 12 operate in the saturation region.Vout=Vin−Vb  (2)
Then, by use of FIGS. 5B and 5C showing a relation of voltages and electric currents of the amplifying transistor 11 and the biasing transistor 12, the operating point of the source follower circuit will be described. For more detail, a case that the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is the same value as the voltage Vgs1 between the gate and the source of the biasing transistor 12 will be described by use of FIG. 5B. Then, a case that the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is a different value which is different from the voltage Vgs2 between the gate and the source of the biasing transistor 12, and for example, the biasing transistor 12 operates in a linear region will be described by use of FIG. 5C.
In FIG. 5B, a dotted line 21 shows a relation of a voltage and an electric current when the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is Vb, and a solid line 22 shows a relation of a voltage and a electric current when the voltage Vgs2 between the gate and the source of the biasing transistor 12 is Vb. Also, in FIG. 5C, a dotted line 21 shows a relation of a voltage and a electric current when the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is Vb′, and a solid line 22 shows a relation of a voltage and a electric current when the voltage Vgs2 between the gate and the source of the biasing transistor 12 is Vb.
In FIG. 5B, since the voltage Vgs1 between the gate and source of the amplifying transistor 11 and the voltage Vgs2 between the gate and the source of the biasing transistor 12 are the same values and further, the bias electric potential Vb and the voltage Vgs2 between the gate and the source of the biasing transistor 12 are the same value, the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is the same value as the bias electric potential Vb. That is, Vgs1=Vgs2=Vb is achieved, and as shown in FIG. 5B, the amplifying transistor 11 and the biasing transistor 12 operate in the saturation region. At this time, a relation of the input electric potential Vin and the output electric potential Vout becomes linear.
On the other hand, in FIG. 5C, the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is a different value which is different from the voltage Vgs2 between the gate and the source of the biasing transistor 12. Then, the voltage Vgs2 between the gate and the source of the biasing transistor 12 is the same value as the bias electric potential Vb. Also, it is assumed that the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is a bias electric potential Vb′. In sum, Vgs2=Vb and Vgs1=Vb′ are satisfied, and as shown in FIG. 5C, the amplifying transistor 11 operates in the saturation region, and the biasing transistor 12 operates in the linear region. At this time, a relation of the input electric potential Vin, the output electric potential Vout and the bias electric potential Vb′ satisfies the following equation (3).Vout=Vin−Vb′  (3)
If it is assumed that an electric current flowing when the biasing transistor 12 operates in the linear region is Ib′, Ib′<Ib is satisfied. In sum, Vb′<Vb is satisfied, and values of both the input electric potential Vin and the electric current Ib′ are lessened. Then, the bias electric potential Vb′ is also lessened. At this time, a relation of the input electric potential Vin and the output electric potential Vout becomes non-linear.
Summarizing the foregoing, in the source follower circuit in the steady state, in order to enlarge an amplitude of the output electric potential Vout it is desirable that the bias electric potential Vb is lessened. This is because of the following two reasons.
A first reason is that, as shown in Equation (2), when the bias electric potential Vb is small, the output electric potential Vout, can be enlarged. A second reason is that, in case that a value of the bias electric potential Vb is large, when the input electric potential Vin is lessened, the biasing transistor 12 operates in the linear region. When the biasing transistor 12 operates in the linear region, the relation of the input electric potential Vin and the output electric potential Vout is apt to become non-linear.
In addition, since it is necessary that the biasing transistor 12 is in a conductive state, it is necessary to set a value of the bias electric potential Vb to be a value which is larger than the threshold voltage of the biasing transistor 12.
The operation of the source follower circuit in the steady state has been described until this point and, subsequently, an operation of the source follower circuit in the transient state will be described by use of FIGS. 6A-B.
The source follower circuit shown in FIGS. 6A-B is of a structure which was designed by adding a capacity device 15 to the circuit of FIG. 5A. One terminal of the capacity device 15 is connected to the source region of the amplifying transistor 11, and the other terminal is connected to a power supply line 16. A ground electric potential Vss is applied to the power supply line 16.
An electric potential difference between both electrodes of the capacity device 15 becomes identical to the output electric potential Vout of the source follower circuit. Here, by use of FIG. 6A, an operation in case of Vout<Vin−Vb will be described, and then, by use of FIG. 6B, an operation in case of Vout<Vin−Vb will be described.
Firstly, by use of FIG. 6A, an operation of the source follower circuit in the steady state in case of Vout<Vin−Vb will be described.
In FIG. 6A, at a time point of t=0, a value of the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is larger than a value of the voltage Vgs2 between the gate and the source of the biasing transistor 12. Therefor, a large electric current flows through the amplifying transistor 11 and electric charge is rapidly held in the capacity device 15. Then, the output electric potential Vout is enlarged, and a value of the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is reduced.
Then, based upon the passage of time (t=t1, t1>0), when the voltage Vgs1 between the gate and the source of the amplifying transistor 11 becomes equal to the bias electric potential Vb, it falls in the steady state. At this time, the relation of the output electric potential Vout, the input electric potential Vin and the bias electric potential Vb satisfy the above-described Equation (2).
Summarizing the foregoing, in case of Vout<Vin−Vb, since the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is larger than the bias electric potential Vb, a large electric current flows through the amplifying transistor 11, and electric charge is rapidly held in the capacity device 15. Therefor, time for holding a predetermined electric charge in the capacity device 15, in other words, time necessary for writing a signal to the capacity device 15 may be shortened.
Then, by use of FIG. 6B, an operation of the source follower circuit in the transient state in case of Vout<Vin−Vb will be described.
In FIG. 6B, at a time point of t=0, the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is of a smaller value than the threshold voltage of the amplifying transistor 11. Therefor, the amplifying transistor 11 is in a non-conductive state. Then, electric charges which were stored in the capacity device 15 flow in a direction of the ground electric potential Vss through the biasing transistor 12, and are finally discharged. At this time, since the voltage Vgs2 between the gate and the source of the biasing transistor 12 is the same value as the bias electric potential Vb, a electric current flowing through the biasing transistor 12 becomes Ib.
Then, based upon the passage of time (t=T1, t1>0), the output electric potential Vout is lessened, and the voltage Vgs1 between the gate and the source of the amplifying transistor 11 is enlarged. Then, when the voltage Vgs1 between the gate and the source of the amplifying transistor 11 becomes equal to the bias electric potential Vb, it falls in the steady state. At this time, the relation of the output electric potential Vout the input electric potential Vin and the bias electric potential Vb satisfies the above-described Equation (2). In addition, in the steady state, the output electric potential Vout is maintained to be a constant value, and electric charges do not flow through the capacity device 15. Then, the electric current Ib flows through the amplifying transistor 11 and the biasing transistor 12.
Summarizing the foregoing, in case of Vout>Vin−Vb, time for holding a predetermined electric charge in the capacity device 15, in other words, time for writing a signal to the capacity device 15 is dependent upon the electric current Ib flowing through the biasing transistor 12. Then, the electric current Ib is dependent upon the bias electric potential Vb. Accordingly, in order to shorten the time for writing the signal to the capacity device 15 by enlarging the electric current Ib, there occurs a necessity to enlarge the bias electric potential Vb.
In addition, as a method for compensating variation of a threshold voltage of a transistor, there is a method that the compensation is carried out by viewing the variation by an output of a circuit to which a signal was inputted and thereafter, by giving feed back of the variation to an input side (e.g., see, Non-Patent Document 1). [Non-Patent Document 1] H. Sekine at al, “Amplifier Compensation Method for a Poly-Si TFT LCLV with an Integrated Data-Driver”, IDRC'97, p. 45-48.
The operation of the above-described source follower circuit is carried out on the assumption that characteristics of the amplifying transistor 11 and the biasing transistor 12 are the same. However, as for the both transistors, overlapped are factors such as variations of gate length (L), gate width (W) and film thickness of a gate insulation film which occur due to difference of manufacturing processes and substrates used and variations of crystalline states of channel forming areas and so on and thereby, there occurs a variation of threshold voltage and mobility of the transistors.
For example, in FIG. 5A, it is assumed that the threshold voltage of the amplifying transistor 11 is 3V; and the threshold voltage of the biasing transistor 12 is 4V, and a variation of 1V occurred. Then, in order to flow the electric current Ib, there occurs a necessity that a voltage which is 1V lower than the voltage Vgs2 between the gate and the source of the biasing transistor 12 to the voltage Vgs1 between the gate and the source of the amplifying transistor 11. In sum, Vgs1=Vb−1 is satisfied. Then, Vout=Vin−Vgs1=Vin−Vb+1 is satisfied. In sum, when there occurs a variation of even 1V in the threshold voltages of the amplifying transistor 11 and the biasing transistor 12, a variation occurs also in the output electric potential Vout.